Dynamic random access memories (DRAMs) are lower in cost than static random access memories (SRAMs). Therefore, DRAMs are often used in personal computers (PC) and large-scale computers.
In a DRAM, an interval between a write command and a read command may be a significant factor and may be called a write-to-read turn around time. The write-to-read turn around time may be an important parameter in a write operation and may have an effect on bus efficiency.
FIG. 1 shows a conventional timing diagram when write and read commands of a conventional DRAM are successive.
An exemplary write latency of a double data rate (DDR) synchronous DRAM (SDRAM) is 10 clock cycles. The write latency may be defined as the delay time between a write command and its finished execution. In one example, a write command of a bank begins execution and two data (DDR) are inputted in the next clock.
Conventionally, a DDR SDRAM uses a 2-bit prefetch scheme. Thus, the DDR SDRAM performs a write operation after receiving two serial input data and arranges the data in parallel.
A column selection signal (CSL) for writing data to a bitline sense amplifier (BL S/A) and a cell may be generated in a second clock cycle to write the data to the memory bank. The CSL signal generated in the second clock may be disabled in a third clock cycle in which a precharge operation for an internal data bus is performed. The internal data bus, which receives a previous write command to transition from a high level to a low level, may be precharged during a clock cycle.
Since the internal bus is shared between different banks, it may be precharged before a read command of a different bank can be executed. Therefore, the read command of the different bank may be applied in a fourth clock cycle after a write command is applied. In FIG. 1, a CAS latency of the read is exemplarily set to “3”.
As shown in FIG. 1, there is an interval of four cycles between write and read commands. Further, FIG. 1 shows an interval of five clock cycles between data transfers for read and write command executions. The shared data bus is inactive during these intervals between data transfers, and therefore inefficient. System applications incorporating frequent read-to-write commands are particularly inefficient.